ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 226

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2549N–AVR–05/11
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 22-5.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 22-6.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 22-7.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 22-8.
UCPOLn
UCSZn2
0
1
UPMn1
0
0
0
0
1
1
1
1
0
0
1
1
UPMn Bits Settings
USBS Bit Settings
UCSZn Bits Settings
UCPOLn Bit Settings
USBSn
Transmitted Data Changed (Output of
0
1
Falling XCKn Edge
Rising XCKn Edge
UCSZn1
UPMn0
TxDn Pin)
0
0
1
1
0
0
1
1
0
1
0
1
ATmega640/1280/1281/2560/2561
UCSZn0
0
1
0
1
0
1
0
1
Received Data Sampled (Input on RxDn
Enabled, Even Parity
Enabled, Odd Parity
Stop Bit(s)
Parity Mode
Reserved
1-bit
2-bit
Disabled
Falling XCKn Edge
Rising XCKn Edge
Character Size
Pin)
Reserved
Reserved
Reserved
5-bit
6-bit
7-bit
8-bit
9-bit
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