SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 149

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 21-6.
21.6.6.3
6289D–ATARM–3-Oct-11
Mode
Attribute Memory
Common Memory
I/O Mode
True IDE Mode
Alternate True IDE Mode
Standby Mode or
Address Space is not
assigned to CF
Alternate Status Read
Control Register
Drive Address
Data Register
Read/Write Signals
Task File
CFCE1 and CFCE2 Truth Table
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the Static Memory Controller section.
In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command
signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deac-
tivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are
driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated.
21-4 on page 150
Attribute memory mode, common memory mode and I/O mode are supported by setting the
address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values.
For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the
Static Memory Controller section.
CFCE2
NBS1
NBS1
NBS1
1
1
1
1
0
0
1
CFCE1
demonstrates a schematic representation of this logic.
NBS0
NBS0
NBS0
0
0
0
0
1
1
1
16 bits
16 bits
16 bits
16bits
DBW
8 bits
8 bits
8 bits
8 bits
Don’t
Care
–
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Even Byte on D[7:0]
Comment
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Access to Odd Byte on D[7:0]
Access to Odd Byte on D[7:0]
AT91SAM9R64/RL64
–
SMC Access Mode
Byte Select
Byte Select
Byte Select
Byte Select
Don’t Care
–
Figure
149