SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 664
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 664 of 903
- Download datasheet (13Mb)
Figure 39-4. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1
Figure 39-5. TFT Panel Timing (Line Expanded View), CLKMOD=1
664
LCDHSYNC
LCDVSYNC
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDOTCK
LCDVSYNC
LCDHSYNC
LCDDEN
LCDDOTCK
LCDDEN
LCDDEN
AT91SAM9R64/RL64
LCDD
LCDD
LCDD
VHDLY+1
VHDLY+1
Vertical Back Porch = VBP Lines
VHDLY+1
--------------------------- -
f
LCDVSYNC
Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation:
where:
In STN Mode:
1
• HOZVAL determines de number of LCDDOTCK cycles per line
• LINEVAL determines the number of LCDHSYNC cycles per frame, according to the
HPW+1
HPW+1
expressions shown below:
(VPW+1) Lines
=
⎛
⎝
VHDLY
-------------------------------------------------------------------------------------------------------------------- -
HBP+1
HBP+1
HOZVAL
+
1 PCLK
HPW
1 PCLK
=
Horizontal_display_size
-------------------------------------------------------------- - 1
+
Line Period
Line Period
f
HBP
LCDDOTCK
Number_data_lines
Frame Period
1/2 PCLK 1/2 PCLK
+
1/2 PCLK 1/2 PCLK
HOZVAL
+
HOZVAL+1
HFP
HOZVAL+1
–
+
5
⎞ VBP
⎠
(
+
LINEVAL
Vertical Fron t Porch = VFP Lines
+
VFP
6289D–ATARM–3-Oct-11
HFP+1
HFP+1
+
1
)
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