SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 196

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.13 Asynchronous Page Mode
22.13.1
Figure 22-34. Page Mode Read Protocol (Address MSB and LSB are defined in
6289D–ATARM–3-Oct-11
Protocol and Timings in Page Mode
A[MSB]
D[31:0]
A[LSB]
MCK
NRD
NCS
The SMC supports asynchronous burst reads in page mode, providing that the page mode is
enabled in the SMC_MODE register (PMEN field). The page size must be configured in the
SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t
quent accesses to the page (t
enables the user to define different read timings for the first access within one page, and next
accesses within the page.
Table 22-7.
Notes:
Figure 22-34
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
Page Size
4 bytes
8 bytes
16 bytes
32 bytes
1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
NCS_RD_PULSE
shows the NRD and NCS timings in page mode access.
Page Address and Data Address within a Page
tpa
Page Address
A[25:2]
A[25:3]
A[25:4]
A[25:5]
sa
) as shown in
(1)
NRD_PULSE
tsa
Table
Figure
22-7.
Data Address in the Page
A[1:0]
A[2:0]
A[3:0]
A[4:0]
Table
22-34. When in page mode, the SMC
AT91SAM9R64/RL64
NRD_PULSE
22-7)
pa
tsa
) takes longer than the subse-
(2)
196