SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 712

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.6.2.1
40.6.2.2
712
AT91SAM9R64/RL64
AC97 Controller Setup
Transmit Operation
The following operations must be performed in order to bring the AC’97 Controller into an oper-
ating state:
The application must perform the following steps in order to send data via a channel to the AC97
Codec:
Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically
set by the AC’97 Controller which allows the application to start a new write action. The applica-
tion can also wait for an interrupt notice associated with TXRDY in order to send data. The
interrupt remains active until TXRDY flag is cleared..
1. Enable the AC97 Controller clock in the PMC controller.
2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register
3. Configure the input channel assignment by controlling the AC’97 Controller Input
4. Configure the output channel assignment by controlling the AC’97 Controller Input
5. Configure sample width for Channel A and Channel B by writing the SIZE bit field in
6. Configure data Endianness for Channel A and Channel B by writing CEM bit field in
7. Configure the PIO controller to drive the RESET signal of the external Codec. The
8. Enable Channel A and/or Channel B by writing CEN bit field in AC97C_CAMR and
• Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status
• Write data to the AC’97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
Register (AC97_CxSR). x being one of the
(AC97C_MR).
Assignment Register (AC97C_ICA).
Assignment Register (AC97C_OCA).
AC97C Channel A Mode Register (AC97C_CAMR) and AC97C Channel B Mode Reg-
ister (AC97C_CBMR). The application can write 10, 16, 18,or 20-bit wide PCM samples
through the AC’97 interface and they will be transferred into 20-bit wide slots.
AC97C_CAMR and AC97C_CBMR registers. Data on the AC-link are shifted MSB first.
The application can write little- or big-endian data to the AC’97 Controller interface.
RESET signal must fulfill external AC97 Codec timing requirements.
AC97C_CBMR registers.
2
channels.
6289D–ATARM–3-Oct-11