SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 658

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 39-7.
39.5.2.6
658
Address
00
01
...
FE
FF
AT91SAM9R64/RL64
Intensity_bit_0
Intensity_bit_1
Intensity_bit_254
Intensity_bit_255
Dithering
Lookup Table Structure in the Memory
access is allowed (the 16 MSB of the bus are not used). For the detailed memory map, see
Table 39-13 on page
The lookup table contains 256 16-bit wide entries. The 256 entries are chosen by the program-
mer from the 2
For the structure of each LUT entry, see
In STN Monochrome, only the four most significant bits of the red value are used (16 gray
shades). In STN Color, only the four most significant bits of the blue, green and red value are
used (4096 colors).
In TFT mode, all the bits in the blue, green and red values are used (32768 colors). In this mode,
there is also a common intensity bit that can be used to double the possible colors. This bit is the
least significant bit of each color component in the LCDD interface (LCDD[18], LCDD[10],
LCDD[2]). The LCDD unused bits are tied to 0 when TFT palletized configurations are used
(LCDD[17:16], LCDD[9:8], LCDD[1:0]).
The dithering block is used to generate the shades of gray or color when the LCD Controller is
used with an STN LCD Module. It uses a time-based dithering algorithm and Frame Rate Con-
trol method.
The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the dis-
play an appearance of multiple shades. In order to reduce the flicker noise caused by turning on
and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the
pattern of adjacent pixels every frame. This algorithm is expressed in terms of Dithering Pattern
registers (DP_i) and considers not only the pixel gray level number, but also its horizontal
coordinate.
Table 39-8
Table 39-8.
Gray Level
15
14
13
12
11
10
9
shows the correspondences between the gray levels and the duty cycle.
Blue_value_0[4:0]
Blue_value_1[4:0]
Blue_value_254[4:0]
Blue_value_255[4:0]
16
Dithering Duty Cycle
possible combinations.
677.
Data Output [15:0]
Duty Cycle
1
6/7
4/5
3/4
5/7
2/3
3/5
Table
Green_value_0[4:0]
Green_value_1[4:0]
Green_value_254[4:0]
Green_value_255[4:0]
39-7.
Pattern Register
-
DP6_7
DP4_5
DP3_4
DP5_7
DP2_3
DP3_5
Red_value_0[4:0]
Red_value_1[4:0]
Red_value_254[4:0]
Red_value_255[4:0]
6289D–ATARM–3-Oct-11