SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 19

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.2
6289D–ATARM–3-Oct-11
Matrix Masters
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The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that
each master can perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 7-1.
Master 0
Master 1
Master 2
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–
DSP Instruction Extensions
5-Stage Pipeline Architecture:
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4-Kbyte Data Cache, 4-Kbyte Instruction Cache
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Write Buffer
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Standard ARM v4 and v5 Memory Management Unit (MMU)
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Bus Interface Unit (BIU)
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ARM High-performance 32-bit Instruction Set
Thumb High Code Density 16-bit Instruction Set
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
Data Memory (M)
Register Write (W)
Virtually-addressed 4-way Associative Cache
Eight words per line
Write-through and Write-back Operation
Pseudo-random or Round-robin Replacement
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
Software Control Drain
Access Permission for Sections
Access Permission for large pages and small pages can be specified separately for
each quarter of the page
16 embedded domains
Arbitrates and Schedules AHB Requests
Separate Masters for both instruction and data access providing complete Matrix
system flexibility
Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
List of Bus Matrix Masters
DMA Controller
USB Device High Speed DMA
LCD Controller DMA
AT91SAM9R64/RL64
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