SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 462

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 34-23. Timeguard Operations
34.6.3.11
6289D–ATARM–3-Oct-11
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
TXD
Receiver Time-out
Start
Bit
D0
D1
Table 34-7
in relation to the function of the Baud Rate.
Table 34-7.
The Receiver Time-out provides support in handling variable-length frames. This feature detects
an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel
Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an
end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at
0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR
remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO.
This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user
can either:
D2
• Stop the counter clock until a new character is received. This is performed by writing the
Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state
D3
D4
D5
Baud Rate
indicates the maximum length of a timeguard period that the transmitter can handle
115200
Bit/sec
14400
19200
28800
33400
56000
57600
1 200
9 600
D6
Maximum Timeguard Length Depending on Baud Rate
D7
Parity
Bit
Stop
Bit
TG = 4
Start
Bit
D0
Bit time
69.4
52.1
34.7
29.9
17.9
17.4
833
104
8.7
µs
D1
D2
D3
AT91SAM9R64/RL64
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Timeguard
212.50
26.56
17.71
13.28
8.85
7.63
4.55
4.43
2.21
ms
TG = 4
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