SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 575

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.3.3.3
Table 37-1.
Notes:
37.3.3.4
37.3.3.5
6289D–ATARM–3-Oct-11
BTSIZE, SADDR reloaded
with BTSIZE reloaded and
with BTSIZE reloaded and
buffer of a multiple buffer
with contiguous DADDR
with contiguous SADDR
and DADDR contiguous
1) Single Buffer or Last
2) Multi Buffer transfer
3) Multi Buffer transfer
4) Multi Buffer transfer
5) Multi Buffer transfer
6) Multi Buffer transfer
7) Multi Buffer transfer
8) Multi Buffer transfer
with DADDR reloaded
with SADDR reloaded
BTSIZE, SADDR and
10) Automatic mode
11) Automatic mode
contiguous DADDR
contiguous SADDR
9) Automatic mode
BTsize is reloaded
channel is stalling
DADDR reloaded
with LLI support
Transfer Type
1. USR means that the register field is manually programmed by the user.
2. CONT means that address are contiguous.
3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must manu-
4. Channel stalled is true if the relevant BTC interrupt is not masked.
5. LLI means that the register field is updated with the content of the linked list item.
transfer
ally program the value.
Programming DMAC for Multiple Buffer Transfers
Replay Mode of Channel Registers
Contiguous Address Between Buffers
Multiple Buffers Transfer Management Table
AUTO
During automatic replay mode, the channel registers are reloaded with their initial values at the
completion of each buffer and the new values used for the new buffer. Depending on the row
number in
DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at
the start of a buffer transfer.
In this case, the address between successive buffers is selected to be a continuation from the
end of the previous buffer. Enabling the source or destination address to be contiguous between
0
0
0
0
0
0
1
1
1
1
1
SRC_REP
–
–
0
–
–
1
–
0
0
1
1
Table 37-1 on page
DST_REP
–
0
–
–
1
–
0
–
0
1
0
SRC_DSCR
575, some or all of the DMAC_SADDRx, DMAC_DADDRx,
1
0
1
0
0
1
0
1
1
1
1
DST_DSCR
1
1
0
0
1
0
1
0
1
1
1
BTSIZE
AT91SAM9R64/RL64
USR
REP
REP
REP
REP
REP
LLI
LLI
LLI
LLI
LLI
SADDR
CONT
CONT
CONT
USR
REP
REP
REP
LLI
LLI
LLI
LLI
DADDR
CONT
CONT
CONT
CONT
USR
REP
REP
LLI
LLI
LLI
LLI
Fields
Other
USR
REP
REP
REP
LLI
LLI
LLI
LLI
LLI
LLI
LLI
575