SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 458
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 458 of 903
- Download datasheet (13Mb)
Figure 34-18. ASK Modulator Output
Figure 34-19. FSK Modulator Output
34.6.3.6
Figure 34-20. Synchronous Mode Character Reception
6289D–ATARM–3-Oct-11
Uptstream Frequency F0
Uptstream Frequencies
unipolar output
FSK Modulator
ASK Modulator
default polarity
[F0, F0+offset]
unipolar output
default polarity
NRZ stream
NRZ stream
Manchester
Manchester
Synchronous Receiver
encoded
encoded
Output
Output
data
data
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Sampling
Clock
RXD
Txd
Txd
1
1
switches to receiving mode. The demodulated stream is sent to the Manchester decoder.
Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a
user-defined number of bits. The Manchester preamble length is to be defined in accordance
with the RF IC configuration.
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 34-20
Start
illustrates a character reception in synchronous mode.
D0
D1
0
0
D2
D3
D4
0
0
D5
D6
AT91SAM9R64/RL64
D7
Parity Bit
Stop Bit
1
1
458
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