SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 20

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.3
7.4
Table 7-3.
7.5
20
0
1
2
3
4
5
Matrix Slaves
Master to Slave Access
Peripheral DMA Controller (PDC)
AT91SAM9R64/RL64
LCD Controller User Interface
AT91SAM9R64/RL64 Master to Slave Access
UDP High Speed RAM
External Bus Interface
Peripheral Bridge
Masters
Slaves
Internal SRAM
Internal ROM
Table 7-1.
The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own
arbiter, allowing a different arbitration per slave.
Table 7-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
• Next Pointer support, prevents strong real-time constraints on buffer management.
of the processor.
List of Bus Matrix Masters
List of Bus Matrix Slaves
Controller
DMA
Peripheral DMA Controller
ARM926
ARM926 Data
Internal ROM
Internal SRAM
LCD Controller User Interface
UDP High Speed RAM
External Bus Interface (EBI)
Peripheral Bridge
0
X
X
X
X
-
-
™
Device DMA
Instruction
USB HS
X
X
X
X
1
-
-
Controller
DMA
LCD
X
X
X
2
-
-
Peripheral
DMA
X
X
X
3
-
-
-
Instruction
ARM926
X
X
X
X
X
4
-
6289D–ATARM–3-Oct-11
ARM926
Data
X
5
X
X
X
X
-