PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 383

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
13.1.6
B2: The line bit interleaved parity bytes provide a line error monitoring function. In the transmit
direction, the S/UNI-8x155 calculates the B2 values. The calculated code is then placed in the
next frame. In the receive direction, the S/UNI-8x155 calculates the B2 code over the current
frame and compares this calculation with the B2 code receive in the following frame. Receive
B2 errors are accumulated in an error event counter.
K1, K2: The K1 and K2 bytes provide the automatic protection switching channel. The K2
byte is also used to identify line layer maintenance signals. Line RDI is indicated when bits 6,
7, and 8 of the K2 byte are set to the pattern '110'. Line AIS is indicated when bits 6, 7, and 8
of the K2 byte are set to the pattern '111'. In the transmit direction, the S/UNI-8x155 provides
register control for the K1 and K2 bytes. In the receive direction, the S/UNI-8x155 provides
register access to the filtered APS channel. Protection switch byte failure alarm detection is
provided. The K2 byte is examined to determine the presence of the line AIS, or the line RDI
maintenance signals.
D4 - D12: The line data communications channel provides a 576 kbit/s data communications
channel for network element to network element communications. In the transmit direction, the
line DCC byte is inserted from a dedicated 576 kbit/s input, TDCC[7:0], when the channel is
configured for line DCC. In the receive direction, the line DCC is extracted on a dedicated 576
kbit/s output, RDCC[7:0], when the channel is configured for line DCC.
S1: The S1 byte provides the synchronization status byte. Bits 5 through 8 of the
synchronization status byte identifies the synchronization source of the STS-3c/STM-1 signal.
Bits 1 through 4 are currently undefined. In the transmit direction, the S/UNI-8x155 provides
register control for the synchronization status byte. In the receive direction, the S/UNI-8x155
provides register access to the synchronization status byte. The SSTB block also provides
circuitry to detect synchronization status mismatch and unstable alarms.
Z1: The Z1 bytes are located in the second and third STS-1’s locations of an STS-3c/STM-1
and are allocated for future growth.
M1: The M1 byte is located in the third STS-1 locations of a STS-3c/STM-1 and provides a line
far end block error function for remote performance monitoring.
Z2: The Z2 bytes are located in the first and second STS-1’s locations of a STS-3c/STM-1 and
are allocated for future growth. In the transmit direction, Z2 byte is internally generated. The
number of B2 errors detected in the previous interval is inserted. In the receive direction, a legal
Z2 byte value is added to the line FEBE event counter.
Path Overhead Bytes
J1: The Path Trace byte is used to repetitively transmit a 64-byte CLLI message (for
SONET/SDH networks), or a 16-byte E.164 address (for SDH networks). When not used, this
byte should be set to transmit continuous null characters. Null is defined as the ASCII code,
0x00. In the transmit direction, characters can be inserted using the TPOP Path Trace register or
the SPTB block. The register is the default selection and resets to 0x00 to enable the
transmission of NULL characters from a reset state. In the receive direction, the path trace
message is optionally extracted into the 16 or 64 byte path trace message buffer.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
383