PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 66

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
10.1 Receive Line Interface (CRSI)
10.1.1
10
Functional Description
The Receive Line Interface allows direct interface of the S/UNI-8x155 to optical modules
(ODLs) or other medium interfaces. This block performs clock and data recovery on the
incoming 155.52 Mbit/s data stream and SONET/SDH A1/A2 pattern framing.
Clock Recovery
The clock recovery units recovers the clock from each incoming bit serial data stream and is
compliant with SONET and SDH jitter tolerance requirements. The clock recovery units utilize
a low frequency reference clock to train and monitor its clock recovery PLL. Under loss of
transition conditions, the clock recovery unit continues to output a line rate clock that is locked
to this reference for keep alive purposes. The clock recovery unit utilizes a 77.76 MHz
reference clock. The clock recovery unit provides status bits that indicate whether it is locked to
data or the reference and also supports diagnostic loopback and a loss of signal input that
squelches normal input data.
Initially upon start-up, the PLL locks to the reference clock, REFCLK. When the frequency of
the recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock to the
data. Once in data lock, the PLL reverts to the reference clock if no data transitions occur in 96
bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock.
When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the
transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of
transition condition. To meet the Bellcore GR-253-CORE SONET Network Element free-run
accuracy specification, the reference must be within +/-20 ppm. For LAN applications, the
REFCLK accuracy may be relaxed to +/-50 ppm.
The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received SONET/SDH data signal. The total loop
dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance
specified for SONET/SDH equipment by GR-253-CORE (2000). Jitter transfer is measured
using the GR-253-CORE (1995) requirement criteria.
The typical jitter tolerance performance of a S/UNI-8x155 channel is shown in Figure 3 with
the GR-253-CORE jitter tolerance specification limits. The jitter tolerance setup used an
AGILENT HFBR-5905 multi-mode fiber optic transceiver with approximately -10 dBm input
power.
Note that for frequencies below 300Hz, the jitter tolerance is greater than 22 UIpp; 22 UIpp is
the maximum jitter tolerance of the test equipment. The dip in the jitter tolerance curve
between 10 kHz and 30 kHz is due to the clock difference detector.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
66