PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 81

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
10.9.4
10.9.5
10.10 Transmit Line Overhead Processor (TLOP)
10.10.1
10.10.2
10.10.3
10.10.4
Framing and Identity Insert
The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and trace/growth
bytes (J0/Z0) into the STS-3c/STM-1 frame. Framing bit errors may be continuously inserted
under register control for diagnostic purposes.
Scrambler
The Scrambler Block utilizes a frame synchronous scrambler to process the transmit stream
when enabled through an internal register accessed via the microprocessor interface. The
generating polynomial is x
in the references. Note that the framing bytes and the identity bytes are not scrambled. All
zeros may be continuously inserted (after scrambling) under register control for diagnostic
purposes.
The Transmit Line Overhead Processor (TLOP) provides line level alarm signal insertion, and
line BIP-24 insertion (B2). In addition, it inserts the line data communication provided serially
on the transmit DCC inputs.
APS Insert
The APS Insert Block inserts the two automatic protection switch (APS) channel bytes in the
Line Overhead (K1 and K2) into the transmit stream when enabled by an internal register.
Data Link Insert
The Data Link Insert Block inserts the line data communication channel (DCC) (bytes D4 to
D12) into the STS-3c/STM-1 stream when enabled by an internal register. The D4 to D12 bytes
are input serially using the associated TDCC signal at a nominal 576 kbit/s rate. Timing for
upstream processing of the line DCC is provided by the TDCLK output. TDCLK is derived
from a 2.16 MHz clock that is gapped to yield an average frequency of 576 kHz.
Line BIP Calculate
The Line BIP Calculate Block calculates the line BIP-24 error detection code (B2) based on the
line overhead and synchronous payload envelope of the transmit stream. The line BIP-24 code
is a bit interleaved parity calculation using even parity. Details are provided in the references.
The calculated BIP-24 code is inserted into the B2 byte positions of the following frame. BIP-
24 errors may be continuously inserted under register control for diagnostic purposes.
Line RDI Insert
The Line RDI Insert Block controls the insertion of line remote defect indication. Line RDI
insertion is enabled through register control. Line RDI is inserted by transmitting the code 110
(binary) in bit positions 6, 7, and 8 of the K2 byte contained in the transmit stream.
7
+ x
6
+ 1. Precise details of the scrambling operation are provided
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
81