PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 43

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
9.1
9
Pin Description
Serial Line Side Interface Signals
Pin Name
SPECLV
SDTTL
RXD[0]+
RXD[0]-
RXD[1]+
RXD[1]-
RXD[2]+
RXD[2]-
RXD[3]+
RXD[3]-
RXD[4]+
RXD[4]-
RXD[5]+
RXD[5]-
RXD[6]+
RXD[6]-
RXD[7]+
RXD[7]-
SD[0]
SD[1]
SD[2]
SD[3]
SD[4]
SD[5]
SD[6]
SD[7]
Type
Differential
PECL Input
PECL Input
Input
Input
Pin
No.
F2
E1
H1
H2
K1
K2
M2
M1
AA2
AA3
AC2
AC1
AE2
AE1
AH2
AG2
G3
J5
K3
M3
Y3
AC3
AE3
AG3
AJ19
AJ17
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Function
The serial line PECL signal voltage select (SPECLV) selects
between 3.3V PECL signaling and 5V PECL signaling for the
serial line interface PECL inputs (RXD[7:0]+/- and SD[7:0]).
When SPECLV is low, the PECL inputs expect a 5V PECL
signal. When SPECLV is high, the PECL inputs expect a 3.3V
PECL signal.
Please refer to the Operation section for a discussion of PECL
interfacing issues.
The signal detect voltage select (SDTTL) selects between
PECL signaling and TTL signal for the signal detector inputs
(SD[7:0]). When SDTTL is low, the signal detect inputs expect
PECL signal levels. When SDTTL is high, the signal detect
inputs expect TTL signal level.
Please refer to the Operation section for a discussion of PECL
interfacing issues.
The receive differential data PECL inputs (RXD[7:0]+/-)
contain the NRZ bit serial receive stream for each channel.
The receive clock is recovered from the RXD+/- bit stream.
Each differential input is terminated with an internal 100 ohm
resistor. Please refer to the Operation section for a discussion
of PECL interfacing issues.
The receive signal detect PECL inputs (SD[7:0]) indicates the
presence of valid receive signal power from the Optical
Physical Medium Dependent Device for each channel.
When SDTTL is low, a PECL logic high indicates the presence
of valid data. A PECL logic low indicates a loss of signal.
When SDTTL is high, a TTL logic high indicates the presence
of valid data. A TTL logic low indicates a loss of signal.
Please refer to the Operation section for a discussion of PECL
interfacing issues
Released
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