PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 397

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
The 8-byte channel FIFO is used to handle fixed phase variations between channels caused by
the serial line interface PISO blocks. Each PISO generates an upstream TCLK from the serial
transmit clock using a free running divide-by-8 counter. Since each PISO can generate a TCLK
which is exactly the same frequency, but with a different phase offset, the channel FIFO is used
to cross clock domains between channels. The channel FIFO should reset using CHFRST to
center the read and write pointers when the APS link is configured.
The diagram in Figure 29 shows the structure of a transmit APS link. Each channel may be
configured using the PROCM register in Figure 28 to send receive path information or transmit
path information over the APS link. The transmit APS link has a four-to-one correlation
between channel and APS link. That is, four channel’s APS information is passed to the other
S/UNI-8x155 device on a fixed APS link. Selection between different channels is performed on
the receive side of the APS link. The TAOP block performs BIP calculation and SONET
scrambling functions for the transmit APS stream. The PISO block generates the 622.08 Mbit/s
serial stream for the interface.
Figure 29 Transmit APS Link
When passing receive path over the transmit APS link, the STAL block performs pointer
processing to handle frequency offsets and jitter variations between the recovered clock and the
synthesized 622.08 MHz clock from the CSU. In order to process the pointer, the RPOP block
must interpret the STS-3c/STM-1 pointer for the STAL block. When the receive path stream
becomes invalid (due to various SONET alarms including LOP, LOS, PAIS, LOPC, AISC), path
AIS is forced over the transmit APS link.
The diagram in Figure 30 shows the structure of a receive APS link. Each receive APS link
uses a DRU to recover the data from the incoming 622Mbit/s stream. The DRU will track high
frequency jitter and low frequency wander of the incoming serial stream. The APS FIFO is
used to handle the phase variation between the APS serial stream and the synthesized
622.08 MHz clock from the CSU which is used to generate the transmit serial data stream. The
APS FIFO reset FRST should be toggled when ROOLV of either CSU in the two S/UNI-8x155
devices indicate a CSU has lost lock or after a system reset. The APS FIFO interrupt FERRI
will indicate when the FIFO has corrupted data due to an overrun or an underrun.
Figure 30 Receive APS Link
RXA[4*y+0]
RXA[4*y+1]
RXA[4*y+2]
RXA[4*y+3]
TXA[4*y+0]
TXA[4*y+1]
TXA[4*y+2]
TXA[4*y+3]
RAOP
4
4
4
TAOP
SIPO
CSU 622MHz
PISO
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
FIFO
APS
ASPO[y]+/-
CSU 622MHz
DRU
APSI[y]+/-
Released
397