PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 392

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
13.10 WAN Synchronization (WANS Block)
13.11 Loopback Operation
The transmit clock in a public UNI must conform to SONET/SDH Network Element (NE)
requirements specified in Bellcore GR-253-CORE. These requirements include jitter
generation, short term clock stability, phase transients during synchronization failure, and
holdover. The 77.76 MHz clock source is typically a VCO (or temperature compensated
VCXO) locked to a primary reference source for public UNI applications. The accuracy of this
clock source should be within ±20 ppm of 77.76 MHz to comply with the SONET/SDH
network element free-run accuracy requirements. The S/UNI-8x155 WANS block can be used
to implement the system timing reference.
The transmit clock in a private UNI or a private NNI may be locked to an external reference or
may free-run. The simplest implementation requires an oscillator free-running at 77.76 MHz.
Source timed operation is selected by clearing the LOOPT bit of the channel’s Master
Configuration register. REFCLK is multiplied by 2 to become the 155.52 MHz transmit clock.
REFCLK must be jitter free. The source REFCLK is also internally used as the clock recovery
reference during receive loss of transition conditions.
Internally loop timed operation is used for private UNIs and private NNIs that require
synchronization to the recovered clock. This mode is selected by setting the LOOPT bit of the
channel’s Master Control register to logic one. Normally, the transmit clock is locked to the
receive data. In the event of a loss of signal/transition condition, the transmit clock is
synthesized from REFCLK.
Externally loop timed operation makes use of the WAN Synchronization block capabilities.
This mode can be achieved when the channel’s LOOPT is set to logic zero. The timing loop is
achieved at the system level, through a microprocessor, an external VCXO and back through the
REFCLK input. This mode allows an S/UNI-8x155 to meet Bellcore wander transfer and
holdover stability requirements.
The WANS provides a means to implement a Stratum 3 or lower system timing reference with a
minimum amount of external circuitry. The WANS implements a phase detector necessary to
create a digital control PLL.
The S/UNI-8x155 supports five loopback functions for each channel: path loopback, line
loopback, data diagnostic loopback, parallel diagnostic loopback and serial diagnostic loopback.
Each channel's loopback modes operate independently. The loopback modes are activated by the
PDLE, SLLE, DLE, DPLE and SDLE bits contained in the channel’s Master Configuration
registers.
The line loopback, see Figure 23, connects the high speed receive data and clock to the high
speed transmit data and clock, and can be used for line side investigations (including clock
recovery and clock synthesis). While in this mode, the entire receive path is operating normally
and cells can be received through the FIFO interface.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
392