PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 411

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
14.1 Transmit ATM UTOPIA Level 3 System Interface
14
TADR[2:0]
DAT[31:0]
Functional Timing
All functional timing diagrams assume that polarity control is not being applied to input and
output data and clock lines (i.e. polarity control bits in the S/UNI-8x155 registers are set to their
default states).
The ATM UTOPIA Level 3 System Interface is compatible with the UTOPIA Level 3
specification (see References). The S/UNI-8x155 only supports the 32-bit mode of operation.
The Transmit UTOPIA Level 3 System Interface Timing diagram (Figure 40) illustrates the
operation of the system side transmit FIFO interface. Assertion of the transmit cell available
output, TCA, indicates that there is space available in the transmit FIFO for at least one ATM
cell structure. Deassertion of TCA occurs when the FIFO is filled with the number of ATM
cells indicated by the register bits FIFODP[1:0]. TCA will only deassert one clock cycle after
TSOC is sampled high and may assert at any time. If the TCA is configured to deassert early
before the FIFO is truly full, the FIFO will accept additional cells even if TCA is inactive. TCA
will be deasserted for polling cycles during the first two cycles of a cell transfer for the phy
being transferred. That is, during transferring a cell it might say it has no more room even if it
does. This prevents a false positive on TCA before the FIFO fill level can be re-evaluated.At
any time, if the upstream does not have a cell to write, it must deassert TENB.
PHY selection occurs by setting the TADR[2:0] bus with the PHY address when TENB changes
from a high to a low value. In the example, a 56-byte ATM cell structure written to PHY #2
which reports that the FIFO is full after the start of the cell is written into the FIFO. The PHY
channels are polled and PHY #0 reports it can accept at least one ATM cell. A cell is written
into PHY #0 which is not full since the transmit cell available TCA does not deassert after the
start of the ATM cell is written into the FIFO.
TSOC must be high during the first byte of the ATM cell structure and must be present for the
start of each cell. Thus, TSOC will mark the word with the H1 to H4 bytes. When TSOC is
asserted and the previous byte transferred was not the end of an ATM cell structure, the system
interface realigns itself to the new timing, and the previous partially transferred cell is dropped.
The length of the cell structure can be configured for 52 and 56 bytes using the CELLFORM
register in TUL3.
Figure 40 Transmit UTOPIA Level 3 System Interface Timing
TPRTY
TFCLK
TSOC
TENB
TCA
2
2
W1
W2
0
2
W3
1
0
X
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
W10
3
X
W11
0
3
W12
1
0
W13
2
1
W14
3
2
0
3
1
0
0
1
W1
0
2
Released
0
W2
3
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