PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 387

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
13.4 Setting ATM Mode of Operation
Last DWORD of an ATM cell is trapped in RUL3 FIFO for 52 bytes cell structure, if RUL3
TRAN is set to 4 , 8, 12, 16 or 24 bytes. For 56 bytes cell structure, the last DWORD of ATM
cell will be trapped if RUL3 TRAN is set to 4 bytes. TMOD is ignored for channels carrying
ATM traffic. When a packet is 1, 2, or 3 bytes smaller than the correct size for a PHY
configured for ATM cells (52/56 bytes), the entire last word on the POS-PHY Level 3 interface
is used as part of the cell, regardless of the state of the TMOD pins. In this case, no errors are
reported by the S/UNI-8x155. Incorrectly sized cells, other than 1,2, or 3 bytes smaller than 52
or 56, cause a TSOCI to assert.
The following sequence of operation should be used to prepare the device for the ATM
operation.
1. Input pin POS_ATMB should be tied low to enable ATM operation. This pin can be
2. Reset the device. This can be done by asserting the RSTB pin or setting the RESET bit in
3. If the TFCLK and RFCLK clock inputs are not stable clocks, wait until these clock inputs
4. Reset the receive and transmit FIFO’s by setting the FIFORST register bits in the TUL3
5. Set the path signal label C2 byte (offset 0x048 and offset 0x054) to 0x13 to identify ATM
6. Reset the performance monitoring counters by writing a logic zero to the Master Reset and
7. Bit 4 in registers 0x062 (and offset registers) must be set low for UTOPIA Level 3 normal
8. The PATM bits in the RUL3 and TUL3 Channel Mode Configuration registers (0x1028,
overridden in software by writing a logic one to the L3MODEINV bits in the TUL3
(register 0x1010) and RUL3 (register 0x1020).
When using the software override feature, these bits must be set after step (2), as resetting
the device restores the registers to their default values. This feature is useful for building a
single PHY card that can be configured in software as a POS or ATM card.
the Master Reset and ID Register (Register 0x000).
stabilize. Reset the DLL units associated with each clock input (write 0x00 to registers
0x1032 and 0x1036 respectively).
(register 0x1010), RUL3 (register 0x1020) and each TXCP (offset 0x080) and RXCP (offset
0x062) blocks. Keep these bits set for at least 1 ms, then set the bit back to its inactive logic
zero value.
payload data.
Identity register (Register 0x00). TIP remains high as the performance monitoring registers
are loaded, and is set to a logic zero when the transfer is complete.
mode operation.
0x1029, 0x102A, 0x102B, 0x1019, 0x101A, 0x101B and 0x101C) should be set
accordingly.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
387