PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 388

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
13.5 Setting Packet-Over-SONET/SDH Mode of Operation
13.6 Setting SONET or SDH Mode of Operation
9. To reduce power consumption write 0x80 to reserved registers 0x806, 0x906, 0xA06,
The following sequence of operation should be used to prepare the device for the Packet over
SONET/SDH (POS) operation.
1. Input pin POS_ATMB should be tied high to enable POS operation. This pin can be
2. Reset the device. This can be done by asserting the RSTB pin or setting the RESET bit in
3. If the TFCLK and RFCLK clock inputs are not stable clocks, wait until these clock inputs
4. Reset the receive and transmit FIFO’s by setting the FIFORST register bits in the TUL3
5. Set the path signal label C2 byte (offset 0x048 and offset 0x054) to 0x16 to identify POS
6. To reduce power consumption write 0x80 to reserved registers 0x806, 0x906, 0xA06,
7. Reset the performance monitoring counters by writing a logic zero to the Master Reset and
In order to avoid frequent TXFP underrun, the recommended TXFP and TUL3 setting in bytes
are: TXFP TIL=192 bytes, TXFP LWM=200 bytes (register 0x0C3 and offset), TXFP
HWM=204 bytes (register 0x0C4 and offset), TUL3 LWM=96 bytes, TUL3 HWM=172 bytes,
TUL3 burst=32 bytes.
The SONET and SDH standard for optical networking are very similar with only minor
difference in overhead processing. The main difference between the SONET (Bellcore GR-253-
CORE) and SDH (ITU.707) standards lies in the handling of some of the overhead bytes. Other
details, like framing and data payload mappings are equivalent in SONET and SDH.
0xB06, 0xC06, 0xD06, 0xE06, 0xF06.
overridden in software by writing a logic one to the L3MODEINV bits in the TUL3
(register 0x1010) and RUL3 (register 0x1020).
When using the software override feature, these bits must be set after step (2), as resetting
the device restores the registers to their default values. This feature is useful for building a
single PHY card that can be configured in software as a POS or ATM card.
the Master Reset and ID Register (Register 0x000).
stablize. Reset the DLL units associated with each clock input (write 0x00 to registers
0x1032 and 0x1036 respectively).
(register 0x1010), RUL3 (register 0x1020) and each TXFP (offset 0x0C1) and RXFP (offset
0x0A0) blocks. Keep these bits set for at least 1 ms, then set the bit back to its inactive logic
zero value.
payload data.
0xB06, 0xC06, 0xD06, 0xE06, 0xF06.
Identity register (Register 0x00). TIP remains high as the performance monitoring registers
are loaded, and is set to a logic zero when the transfer is complete.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
388