PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 421
PM5380-BI
Manufacturer Part Number
PM5380-BI
Description
Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5380-BI.pdf
(440 pages)
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Document No.: PMC- 2010299, Issue 2
18
Microprocessor Interface Timing Characteristics
T A = -40°C to T J =+125°C, V DDI = 2.5V ± 5%, V DD = 3.3V ± 8%, V AVD = 3.3V ± 5%,
Table 27 Microprocessor Interface Read Access (Figure 48)
Symbol
tSAR
tHAR
tSALR
tHALR
tVL
tSLR
tHLR
tPRD
tZRD
tZINTH
Figure 48 Microprocessor Interface Read Timing
Notes on Microprocessor Interface Read Timing:
1.
2.
3.
4.
(CSB+RDB)
Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference
signal to the 1.4 Volt point of the output.
Maximum output propagation delays are measured with a 100 pF load on the Microprocessor
Interface data bus, (D[7:0]).
A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS
tH
ALR
D[7:0]
A[8:0]
INTB
ALE
, tV
Parameter
Address to Valid Read Set-up Time
Address to Valid Read Hold Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Read Set-up
Latch to Read Hold
Valid Read to Valid Data Propagation Delay
Valid Read Negated to Output Tri-state
Valid Read Negated to Output Tri-state
L
, tS
LR
, and tH
tSalr
tVl
tVl
LR
tSar
are not applicable.
tSlr
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
tPrd
tHalr
VALID
Min
10
10
10
—
—
—
tZrd
5
5
0
5
tHar
tZinth
tHlr
Max
70
20
50
—
—
—
—
—
—
—
Released
ALR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
421
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