PM5364 pmc-sierra, PM5364 Datasheet - Page 129

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

10.7.1
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
For T:S:T switching all sixteen input streams to the CCB must align with each other for
meaningful switching to occur. Subsystem logic is used to generate alignment control for the
ingress streams based on the PP Frame Alignment Delay Register and the egress stream
alignment (EJ0 and System Egress Reference Delay values).
Subsystem logic chooses the correct CMP value for each of the functional blocks and will
ensure that the CMP values are delayed so they arrive at each block at the correct time.
The user has the option of outputting the J0 character once every four frames to denote
multiframe alignment on the system egress output. The first frame of the four-frame multiframe
is specified by EJ0.
Memory Switch Unit (MSU-Lite)
The MSU-Lite is an STS-12 77.76 MHz TelecomBus column switch. Any input column can be
switched to any output column. Control information is switched along with the data byte.
Data entering the MSU-Lite is stored in two alternating pages of memory. Each page contains
one row (1080 bytes) of information. One of these alternating pages is currently filling while the
other page is currently full. Data exiting the MSU-Lite is extracted from the currently full page.
As a consequence the MSU-Lite imposes a nominal switching latency of 1 row (~13.94 µs). The
switching connection memory for the output port contains 13-bit control for each of the
1080 columns in the frame. Dual banks of this control memory are provided to enable hitless
frame boundary switchover.
Any changes to the Switch Control RAM data are written into the off-line page through the
MPIF. When there is a change in the Switch Control RAM pages, the MSU-Lite can copy the
on-line page onto the off-line one. This can also be done by writing to the Interrupt Status and
Memory Page Update Register. While this page copy is happening, data is prevented from being
written into the off-line page, and an interrupt is generated when the off-line page update is
completed. In addition, a change in the connection memory page input, signifying that a change
of the RAM pages is to occur at the next frame boundary, is flagged by an interrupt.
The MSU-Lite supports a bypass mode in which no switching is done. In this mode, each
STS-12 slice bypasses the corresponding MSU-Lite. Bypass of individual MSU-Lite blocks is
not allowed i.e. all eight ingress MSU-Lites must be bypassed together or all eight egress MSU-
Lites must be bypassed together.
The MSU-Lites (#9, #10, #11, and #12) contain the per column EMSU_SEL configuration bit
used to select which of the bi-casted streams is transmitted to the egress data path.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
129