PM5364 pmc-sierra, PM5364 Datasheet - Page 54

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Pin Name
HRALMCLK
HRALMFP
IDATA_4[7]
IDATA_4[6]
IDATA_4[5]
IDATA_4[4]
IDATA_4[3]
IDATA_4[2]
IDATA_4[1]
IDATA_4[0]
IDATA_3[7]
IDATA_3[6]
IDATA_3[5]
IDATA_3[4]
IDATA_3[3]
IDATA_3[2]
IDATA_3[1]
IDATA_3[0]
IDATA_2[7]
IDATA_2[6]
IDATA_2[5]
IDATA_2[4]
IDATA_2[3]
IDATA_2[2]
IDATA_2[1]
IDATA_2[0]
IDATA_1[7]
IDATA_1[6]
IDATA_1[5]
IDATA_1[4]
IDATA_1[3]
IDATA_1[2]
IDATA_1[1]
IDATA_1[0]
Ingress and Egress Byte-Wide TelecomBus Interface (96 pins: 48 Ingress, 48 Egress)
Type
Output
Output
Input
Pin No.
AH33
AJ34
G1
G2
G3
F1
F2
F3
F4
E2
E7
D7
B6
C7
B7
E8
D8
A7
C9
B9
A9
D10
C10
B10
A11
E11
E12
D12
B12
A13
B13
E13
D13
C13
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Function
High Order Receive Path Alarm Clock.
HRALMCLK is used to externally sample HRALM
and HRALMFP.
HRALMCLK is a nominal 20.736MHz clock or
2592-clock pulse at each 125-us. This clock is
derived from a 77.76 MHz clock divided by three
and the low level is gapped by an addition of 6
REFCLK cycles to produce the 20.736 MHz.
During 8 cycles the high duty cycle is 33%.
High Order Receive Path Alarm Frame Pulse.
HRALMFP is used to identify the bit position of
HRALM. HRALMFP is asserted for one
HRALMCLK clock cycles every 125 µs, and
identifies the first alarm position.
HRALMFP is updated on the falling edge of
HRALMCLK.
Ingress Bus Data. The Ingress Bus data, carries
the 32-bit serial STS-48c/STS-36c/STS-
24c/STS-12c/STS-3c/STS-1 SONET payload or
AU4-16c/AU4-12c/AU4-8c/AU4-4c/AU4/AU3/TU3
SDH payload when the device is configured in
STS-48/STM-16 mode or carries the four byte
serial STS-12c/STS-3c/STS-1 SONET payload or
AU4-4c/AU4/AU3/TU3 SDH payload when the
device is configured in quad STS-12/STM-4 mode.
IDATA_N[7] is the most significant bit,
corresponding to bit 1 of each serial word, the bit
received first. IDATA_N[0] is the least significant
bit, corresponding to bit 8 of each serial word, the
bit received last.
IDATA_N[7:0] is sampled on the rising edge of
REFCLK.
Released
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