PM5364 pmc-sierra, PM5364 Datasheet - Page 173

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

13.5.7
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
J0 Synchronization of the STSI in a CHESS System
Any TSE/TBS fabric can be viewed as a collection of different stages. For example, a Time-
Space-Time switch could be constructed with five data path stages:
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The STSIs on the line side of the TUPP 2488 are the equivalent of a TBS switching section.
Note that in some cases, one physical device may serve in two stages, such as SPECTRA 2488
in stages 1 and 5 or TBS in stages 2 and 4. STS-12 frames are pipelined through this fabric in a
regular fashion, under control of a single clock frequency (77.76 MHz). In order to maintain
valid framing for the group of STS-12 streams, the data path devices must be coordinated with
one another. The first step in this coordination is the use of a global frame synchronization pulse
to mark the position of frame boundaries as they enter the fabric. However, since each device in
the system data path sees the STS-12 frames at a different latency than other devices, there must
be a mechanism to account for the individual latencies at different points along the data path.
The most significant source of delay is the cumulative latency of the devices that lie along the
system data path. To accommodate different system arrangements, a synchronization frame
pulse and a programmable frame delay register are used to re-frame the STS-12 streams for
each system data path device. In the TBS, this FIFO is 24-words deep and is controlled by the
RJ0FP pin along with the RJ0DLY register (TUPP 2488 has IJ0 and similar registers to
RJ0DLY). This frame delay register is used to inform the TBS or TUPP 2488 of the latency
between a frame pulse on the RJ0FP/IJ0 pin and the presence of J0 characters in the FIFOs so
that a re-framing mechanism can be triggered at the appropriate time. Because the J0 characters
may lie at different FIFO depths, due to skew between links, this re-framing can be achieved by
realigning the FIFO read pointers to match the J0 positions.
The purpose of the TUPP 2488s CML ALIGN and DMUX FIFOs is similar to the TBS FIFOs.
The depth of the FIFOs is intended to accommodate skew between the arrival time of the J0
character between links of a single TUPP2488 device and between links of different TUPP 2488
devices. The LINE_INGRESS_REF_DLY value and SYSTEM_EGRESS_REF_DLY value
specify an offset from the IJ0 and EJ0 frame pulse inputs to the device, respectively. This
offset, inturn, specifies when the J0 character is read from the CML FIFOs. The reference delay
values must be programmed such that the J0 character is present in the FIFOs at the time
marked by the input frame pulse (referred to as the RXJ0FP marker in the register document)
and associated REF_DLY offset. The TUPP 2488 simplifies the task of determining the correct
REF_DLY values by reporting the difference between when the J0 character is written to the
FIFO and when the RXJ0FP marker initiates a read of the J0 character. The distance value is
reported in the CML Rx Slice Distance Register.
Ingress load devices (e.g. SPECTRA 2488)
Ingress time switch (e.g. TBS or STSI)
Crossbar switch (e.g. TSE)
Egress time switch (e.g. TBS or STSI)
Egress load devices (e.g. SPECTRA 2488)
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
173