PM5364 pmc-sierra, PM5364 Datasheet - Page 85

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
The DMUX FIFO block has four 36 word deep (4x36x9bit) FIFOs with write side logic
ensuring J0 data from the RSEF is written to address 0. The read pointers will naturally wrap
around to the J0 byte location as the FIF0 size divides evenly into the STS-12/STM-4 frame
size.
Each of the four STS-12 channel sets generated by the DMUX_FIFO are aligned to a
programmable offset (LINE_INGRESS_REF_DLY) from the device frame start marker input
IJ0. The offset frame start marker is referred to as RXJ0FP. The alignment distance between the
receive frame pulse J0 marker generated by RSEF (indicates when the J0 character is written
into address zero of the FIFO) and RXJ0FP is measured and can be read out with the
DISTANCE bits in the CML Rx Slice Distance register. The offset is programmed such that the
DISTANCE bits report a FIFO depth that is acceptable for accommodating receive clock jitter,
and for systems containing multiple TUPP 2488 devices, skew between serial streams processed
by different devices.
Loss of alignment is declared when the J0 character is not available in the DEMUX_FIFO at the
expected time (coincident with RXJ0FP). The alignment failure is recorded in the CML Rx
Slice INT_STATUS register. Optionally an interrupt is generated, enabled by the CML Rx Slice
INT_ENABLE register.
A DMUX_FIFO error is indicated and an interrupt is optionally generated whenever the read
and write pointers are within 1 FIFO location of each other. The pointers continuously
increment and are frequency locked so they are only compared when the write pointer wraps
back to the first location in the FIFO.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
85