PM5364 pmc-sierra, PM5364 Datasheet - Page 93

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

10.3.5
10.4
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
If configured for emission of scrambled data, the TSEC applies SONET/SDH scrambling to the
data stream.
The TSEC can be configured to overwrite the data stream with a pseudo random bit sequence
(PRBS) either as a raw stream or with the PRBS within a SONET concatenated SPE, excluding
the path overhead and fixed stuff bytes of the SPE. The TSEC supports PRBS generation of
only concatenated SONET/SDH streams at the line rate: STS-12c, STS-48c. The PRBS
polynomial used is x
The STS48 Line Side Subsystem TX Slice contains two TSEC blocks, one that operates when
the block is configured for STS12 operation and one that operates when the slice is configured
for STS48 operation. The TSEC block addressed is dependent on the STS48_EN bit setting in
the CML Control Register. Configure the STS48_EN bit prior to programming the TSEC block.
Timing FIFO Block (TIM_FIFO)
The TIM_FIFO block consists of an 8*10-bit FIFO. The transmit data from the TSEC is written
to the FIFO synchronous to the 77 MHz core reference clock when in STS12 mode and a 311
MHz reference clock derived from the transmit PISO block when in STS48 mode. The FIFO is
read synchronous to the transmit PISO clock.
The timing FIFO write address is initialized with four while the read address is initialized with
zero. The CENTER bit of the CML TX Slice Config register resets the FIFO write and read
addresses to there initial value. The CENTER register bits are self-clearing, so that a number of
clock cycles after a bit has been set, the CENTER operation will complete, and the bit will be
reset automatically.
A FIFO underrun or overrun is monitored and flagged via status bits in the CML TX Slice
INT_STATUS register. An interrupt is optionally generated depending on the state of the
interrupt enable bits of the CML TX Slice Control register.
ECBI_TX_SLICE Block
The ECBI_TX_SLICE block provides control and status for the RASIO™ CML transmit slice.
SONET/SDH Time Slot Interchange (STSI)
The line ingress interface of TUPP 2488 contains two STSI blocks – one for the Line Ingress
Serial RASIO™ CML working links and one for the Line Ingress Serial RASIO™ CML protect
links. The STSI for the working links is also shared with the Ingress Byte-Wide TelecomBus
Interface.
Similarly, the line egress interface of TUPP 2488 contains two STSI blocks – one for the Line
Egress Serial RASIO™ CML working links and one for the Line Egress Serial RASIO™ CML
protect links. The STSI for the working links is also shared with the Egress Byte-Wide Telecom
Bus Interface.
23
+x
18
+1.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
93