PM5364 pmc-sierra, PM5364 Datasheet - Page 230

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

13.13.5
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
1. Write a logic 1 to the TX_XFER_SYNC bit of the Transmit Status and FIFO Synch
2. Write to the Transmit FIFO Data Low and Transmit FIFO Data High registers. Writing to
3. Read the TX_FI_BUSY bit in the Transmit Status and FIFO Synch Register or wait a
4. Loop back to Step 2 until the entire message has been written in to the FIFO.
When transmitting multiple 32 byte messages, the TX_XFER_SYNC bit does not have to be
written to between each message.
When transmitting a message shorter than 32 bytes, the TX_XFER_SYNC bit should be set
after writing the last byte of the message into the FIFO. This will allow the short message to be
transmitted and move the FIFO to the next 32 byte partition.
Handling the Transmit Header
PAGE Bits
If the IPAGE bits are changed, they are not sent in the header bits until the next frame. They
will be continually sent for each message in subsequent frames until they change again.
USER, LINK and AUX Bits
When any of these bits change they are sent in the header bits of the next message. They will be
continually sent for each subsequent message until they change again.
Bypass Function
TILC transmit function can be disabled by writing a ‘1’ to TX_BYPASS in the Transmit Control
register. When in bypass mode the message FIFO ram is disabled and writes to the transmit
FIFO are ignored.
The TILC functions as a two-stage pipeline in bypass mode.
Receive Inband Link Controller Microprocessor Interface
Message Receive Registers
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•
Register. This will ensure the subsequent writes to the FIFO start at the beginning of a
message.
the Transmit FIFO Data Low register will initiate a transfer of the Transmit FIFO Data
Register into the transmit FIFO.
minimum of 3 REFCLK cycles. If TX_FI_BUSY is a logic 0, continue to step 4. If it is a
logic 1, continue polling the TX_FI_BUSY bit.
Two 16-bit registers (Receive FIFO Data), from which the RX microprocessor reads the 32
bytes of information that have been received in the message payload.
A Receive Control register that is used to enable CRC-16 swizzling (reversal) in the receive
logic for use in diagnostic testing and verification of ILC.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
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