PM5364 pmc-sierra, PM5364 Datasheet - Page 56

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PM5364

Manufacturer Part Number
PM5364
Description
Tupp 2488 Assp Telecom Standard
Manufacturer
pmc-sierra
Datasheet

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Part Number:
PM5364-BI
Manufacturer:
PMC
Quantity:
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Pin Name
IPAIS[4]
IPAIS[3]
IPAIS[2]
IPAIS[1]
EDATA_4[7]
EDATA_4[6]
EDATA_4[5]
EDATA_4[4]
EDATA_4[3]
EDATA_4[2]
EDATA_4[1]
EDATA_4[0]
EDATA_3[7]
EDATA_3[6]
EDATA_3[5]
EDATA_3[4]
EDATA_3[3]
EDATA_3[2]
EDATA_3[1]
EDATA_3[0]
EDATA_2[7]
EDATA_2[6]
EDATA_2[5]
EDATA_2[4]
EDATA_2[3]
EDATA_2[2]
EDATA_2[1]
EDATA_2[0]
EDATA_1[7]
EDATA_1[6]
EDATA_1[5]
EDATA_1[4]
EDATA_1[3]
EDATA_1[2]
EDATA_1[1]
EDATA_1[0]
Type
Input
Output
Pin No.
C6
D9
A12
A15
B28
A29
B29
A30
B30
E33
F32
F33
J34
K32
K33
K34
L32
L33
L34
M33
R33
T34
U32
U31
U33
V33
V31
V32
AB34
AB33
AB32
AC33
AD34
AD33
AD32
AE34
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Function
Ingress High Order Path AIS. The Ingress high
order path alarm bus, IPAIS[4:1], identifies
STS/STM streams on the corresponding ingress
data bus (IDATA[4:1][7:0]) that are in high order
path AIS state. IPAIS[N] is set high when the
stream on IDATA_N[7:0] is in AIS and is set low
when the stream is out of AIS state.
IPAIS[4:1] is sampled on the rising edge of
REFCLK.
Egress Bus Data. The Egress Bus data, carries
the 32-bit serial
STS-48c/STS-36c/STS-24c/STS-12c/STS-3c/STS-
1 SONET payload or AU4-16c/AU4-12c/
AU4-8c/AU4-4c/AU4/AU3/TU3 SDH payload to be
transmitted when the device is configured in
STS-48/STM-16 mode or carries the four byte
serial STS-12c/STS-3c/STS-1 SONET payload or
AU4-4c/AU4/AU3/TU3 SDH payload to be
transmitted when the device is configured in quad
STS-12/STM-4 mode.
EDATA_N[7] is the most significant bit,
corresponding to bit 1 of each serial word, the bit
transmitted first. EDATA_N[0] is the least
significant bit, corresponding to bit 8 of each serial
word, the bit transmitted last.
EDATA_N[7:0] is updated on the rising edge of
REFCLK.
EDATA_N[7:0] pins are implemented with
programmable drive I/O. They are controlled by
VDDOPROG_E.
Released
56

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