PM5364 pmc-sierra, PM5364 Datasheet - Page 57

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Pin Name
EDP[4]
EDP[3]
EDP[2]
EDP[1]
EPL[4]
EPL[3]
EPL[2]
EPL[1]
Type
Output
Output
Pin No.
F34
N32
W34
AE33
G32
N33
W33
AE32
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Function
Egress Bus Data Parity. The Egress Bus data
parity signal, EDP[4:1], carries the parity of the
egress signals. The parity calculation
encompasses the EDATA[N][7:0] bus and
optionally the EJ0J1 [N] and EPL[N] signals.
EJ0J1[N] and EPL[N] can be included in the parity
calculation by setting the EGJ0J1PAREN and
EGPLPAREN register bits in the Parity Control
register high, respectively. Odd parity is selected
by setting the EGODDPAREN register bit in the
same register high and even parity is selected by
setting the EGODDPAREN bit low.
EDP[4:1] is updated on the rising edge of REFCLK.
EDP[4:1] pins are implemented with programmable
drive I/O. They are controlled by VDDOPROG_E.
Egress Bus Payload Active. The Egress Bus
payload active signal, EPL[4:1], identifies the
payload bytes on EDATA[4:1][7:0].
EPL[4:1] identifies the bytes on the egress stream
EDATA[4:1][7:0] that are part of the synchronous
payload envelope. EPL[4:1] is set high during path
overhead and payload bytes and low during
transport overhead bytes.
When the H3 byte contains part of the synchronous
payload envelope due to a negative pointer
justification, EPL[4:1] is set high; when a byte is a
dummy byte due to a positive pointer justification,
EPL[4:1] is set low. Also, EPL[4:1] is set high
during bytes of the two fixed stuff columns in an
STM-1 containing TU3’s, as these stuff bytes are
aligned relative to the VC4’s J1 byte).
EPL[4:1] is updated on the rising edge of REFCLK.
EPL[4:1] pins are implemented with programmable
drive I/O. They are controlled by VDDOPROG_E.
Released
57