PM5364 pmc-sierra, PM5364 Datasheet - Page 90

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

10.2.7
10.2.8
10.3
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Table 5 Inband Message Header Fields
Changes in these bits (received side) will not be processed if the received message CRC-16
indicates an error.
Working/Protect Selection
On the system egress side of TUPP 2488, selection between the working and protect serial
RASIO™ CML links is done using the SEWSEL chip input or top-level registers. Changes in
this chip input or top-level registers are synchronized to the next frame boundary.
On the line ingress side of TUPP 2488, selection between working and protect serial RASIO™
CML links is done at the output of the STSI blocks using the LIWSEL chip input or top-level
registers.
ECBI_RX_SLICE Block
The ECBI_RX_SLICE block provides control and status for the CML receive slice.
CML Transmitter Interface Sub-blocks
The following sections describe the sub-blocks used in the CML transmitter interface.
Field
Name
Valid
Link[1:0]#
Page[1:0]#
User[2:0]#
Aux[7:0]#
Master to Slave (External
NSE/Internal CCB to Internal MSU-
Lite/External SBS)
Message slot contains a message(1) or is
empty(0). If empty this message will not be
put into Rx Message FIFO (other header
information processed as usual)
These bits are optional, intended for devices
which have multiple redundant links. Each
bit either indicates which Link to use,
Working(0) or Protect(1) when sourced from
the master device, or which link is being
used, when sourced from the slave device.
Transmitted immediately.
Each bit indicates which control page to
use, page 1 or 0, two bits, bit 1 for the
ingress MSU/MSU-Lite and bit 0 for the
egress MSU/MSU-Lite. Only transmitted
from the beginning of the first message of
the frame
User defined register bits which may be
read through the microprocessor interface.
Transmitted immediately.
User defined auxiliary register. Transmitted
immediately.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Slave to Master (Internal MSU-
Lite/External SBS to External
NSE/Internal CCB)
Message slot contains a message(1) or is
empty(0). If empty this message will not be
put into Rx Message FIFO (other header
information processed as usual)
These bits are optional, intended for
devices which have multiple redundant
links. Each bit either indicates which Link to
use, Working(0) or Protect(1) when sourced
from the master device, or which link is
being used, when sourced from the slave
device. Transmitted immediately.
Each bit shows current control page in use,
page 1 or 0, two bits, bit 1 for the ingress
MSU/MSU-Lite and bit 0 for the egress
MSU/MSU-Lite. Only transmitted from the
beginning of the first message of the frame.
User defined bits. User[2:0] is sourced from
top-level registers. Transmitted
immediately.
User defined auxiliary register. Transmitted
immediately.
Released
90