PM5364 pmc-sierra, PM5364 Datasheet - Page 232

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

13.14 TUPP 2488 SERDES and CSU Operations
13.15 Receive RASIO™ CML Link Electrical Monitoring
13.15.1
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Before reading any messages, the software may want to check how many messages are
contained in the receive FIFO. This can be done by reading the RX_MSG_LVL[3:0] bits in the
Receive Status and FIFO Synch Register. When reading these bits, the RX_STTS_VALID bit
must also be checked. If RX_STTS_VALID is a logic 1, the RX_MSG_LVL[3:0] bits are valid.
If RX_STTS_VALID is a logic 0, the RX_MSG_LVL[3:0] bits are not valid and this register
should be read again until RX_STTS_VALID is a logic 1.
Receive Message Header Bytes
PAGE, USER. LINK, an AUX Bits
The receive message header is available in the Receive Status and FIFO Synch Register. The
information in the register is only updated when the receive message CRC is correct.
Handling Interrupts
All interrupts are masked on startup, and should not be enabled until the link initializes.
Bypass Function
RILC receive function can be disabled by writing a ‘1’ to RX_BYPASS in the Receive Control
register. When in bypass mode the message FIFO ram is disabled and reads from the receive
FIFO return random data.
The RILC functions as a two-stage pipeline in bypass mode.
Configuration bits for the SERDES and CSU are all described in full in the register description
for TUPP 2488. The recommended default settings should be used for SERDES and CSU.
Each RSEF block incorporates a DC balance monitor, a consecutive identical digit (CID)
detector, and a transition detector. The monitors optionally forces the state machine into the out
of frame alignment condition should the quality of the received data stream degrade. The
contribution of the DC balance / CID / transition monitors to the RSEF state machine is enabled
by setting the CID_TRAN_DC_EN bit to a logic 1. Electrical monitoring is recommended for
links configured for scrambled NRZ mode only (i.e. operating at 622 Mbit/s or 2.488 Gbit/s) as
8b/10b encoded links operating at 777 Mbit/s ensure adequate transitions and DC balance.
DC Balance Monitor
The DC balance monitor has 3 programmable parameters to provide sufficient flexibility in
modeling the external link. The three parameters are the decay period (DECAY_PER), the
decay factor (DECAY_FAC) and the threshold (DC_BAL_THRESH).
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
232