mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 10

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Table 3:
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
1gb_ddr_mobile_sdram_t48m_density__2.fm - Rev. G 07/08 EN
60-Ball VFBGA
G2, G3
G1
H7
G9, G8, G7
F2, F8
H8, H9
J8, J9, K7, K8, K2,
K3, J1, J2, J3, H1,
J7, H2, H3, F7
A8, B7, B8, C7,
C8, D7, D8, E7,
E3, D2, D3, C2,
C3, B2, B3, A2
E8, E2
VFBGA Ball Descriptions
90-Ball VFBGA
G2, G3
G1
H7
G9, G8, G7
K8, K2, F8, F2
H8, H9
J8, J9, K7, K9, K1,
K3, J1, J2, J3, H1,
J7, H2, H3
R8, P7, P8, N7,
N8, M7, M8, L7,
L3, M2, M3, N2,
N3, P2, P3, R2,
A8, B7, B8, C7,
C8, D7, D8, E7,
E3, D2, D3, C2,
C3, B2, B3, A2
L8, L2, E8, E2
LDQS, UDQS
RAS#, CAS#,
UDM, LDM
BA0, BA1
DQ[15:0]
DQ[31:0]
DQS[3:0]
Symbol
(60-ball)
DM[3:0]
(90-ball)
(60-ball)
(90-ball)
(60-ball)
(90-ball)
(60-ball)
(90-ball)
CK, CK#
A[13:0]
A[12:0]
WE#
CKE
CS#
output
output
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Type
10
Clock: CK is the system clock input. CK and CK# are
differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of
CK and the negative edge of CK#. Input and output data is
referenced to the crossing of CK and CK# (both directions of
the crossing).
Clock enable: CKE HIGH activates, and CKE LOW deactivates,
the internal clock signals, input buffers, and output drivers.
Taking CKE LOW enables PRECHARGE power-down and
SELF REFRESH operations (all banks idle), or ACTIVE power-
down (row active in any bank). CKE is synchronous for all
functions except SELF REFRESH exit. All input buffers
(except CKE) are disabled during power-down and self
refresh modes.
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for
external bank selection on systems with multiple banks. CS#
is considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#)
define the command being entered.
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with
that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the
DM loading is designed to match that of DQ and DQS balls.
Bank address inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0 and BA1 also determine which mode register is
loaded during a LOAD MODE REGISTER command.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto-precharge bit
(A10) for READ or WRITE commands, to select one location
out of the memory array in the respective bank. During a
PRECHARGE command, A10 determines whether the
PRECHARGE applies to one bank (A10 LOW, bank selected
by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE REGISTER
command.
Data input/output: Data bus for x16 and x32.
Data strobe: Output with read data, input with write data.
DQS is edge-aligned with read data, center-aligned in write
data. It is used to capture data.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
1Gb: x16, x32 Mobile DDR SDRAM
Description
©2007 Micron Technology, Inc. All rights reserved