mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 74

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Auto Precharge
Concurrent Auto Precharge
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. G 07/08 EN
Care.” After a bank has been precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank. A PRECHARGE command
will be treated as a NOP if there is no open row in that bank (idle state), or if the previ-
ously open row is already in the process of precharging.
Auto precharge is a feature that performs the same individual-bank precharge function
described previously, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent in that it is either enabled or disabled for each indi-
vidual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating
each burst type in “Operations” on page 36. The READ with auto precharge enabled or
WRITE with auto precharge enabled states can each be broken into two parts: the access
period and the precharge period. The access period starts with registration of the
command and ends where the precharge period (or
precharge, the precharge period is defined as if the same burst was executed with auto
precharge disabled and then followed with the earliest possible PRECHARGE command
that still accesses all the data in the burst. For WRITE with auto precharge, the precharge
period begins when
addition, during a WRITE with auto precharge, at least one clock is required during
time. During the precharge period, the user must not issue another command to the
same bank until
This device supports
single WRITE with auto-precharge issued at
delayed until
Bank READ operations with and without auto precharge are shown in Figure 43 on
page 75 and Figure 44 on page 76. Bank WRITE operations with and without auto
precharge are shown in Figure 45 on page 77 and Figure 46 on page 78.
This device supports concurrent auto precharge such that when a READ with auto
precharge is enabled or a WRITE with auto precharge is enabled, any command to
another bank is supported, as long as that command does not interrupt the read or write
data transfer already in process. This feature enables the precharge to complete in the
bank in which the READ or WRITE with auto precharge was executed, without requiring
an explicit PRECHARGE command, thus freeing the command bus for operations in
other banks. During the access period of a READ or WRITE with auto precharge, only
ACTIVE and PRECHARGE commands may be applied to other banks. During the
precharge period, ACTIVE, PRECHARGE, READ, and WRITE commands may be applied
to other banks. In either situation, all other related limitations apply (for example,
contention between READ data and WRITE data must be avoided).
t
RASmin has been satisfied.
t
RP is satisfied.
t
WR ends, with
t
RAS lock-out. In the case of a single READ with auto-precharge or
74
t
WR measured as if auto precharge was disabled. In
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1Gb: x16, x32 Mobile DDR SDRAM
t
RCDmin, the internal precharge will be
t
RP) begins. For READ with auto
t
RAS (MIN), as described for
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Timing Diagrams
t
WR