mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 73

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 42:
PRECHARGE
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. G 07/08 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
Notes:
Bank a,
WRITE
Col b
T0
t DQSS
t DQSS
t DQSS
1. PRE = PRECHARGE.
2.
3. D
4. An interrupted burst of 8 is shown; one data element is written.
5. DQS is required at T4 and T4n to register DM.
6. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access
some specified time (
mines whether one or all banks are to be precharged, and in the case where only one
bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all
banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are treated as a “Don’t
t
D
WR is referenced from the first positive CK edge after the last data-in pair.
b
IN
IN
NOP
D
b = data-in for column b.
T1
b
IN
3
D
b
IN
T1n
NOP
T2
t
RP) after the PRECHARGE command is issued. Input A10 deter-
T2n
73
T3
NOP
t WR
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
1Gb: x16, x32 Mobile DDR SDRAM
NOP
T4
Don’t Care
T4n
(a or all)
T5
PRE
Bank
1
©2007 Micron Technology, Inc. All rights reserved
Timing Diagrams
Transitioning Data
T6
NOP