mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 18

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Table 8:
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
1gb_ddr_mobile_sdram_t48m_density__2.fm - Rev. G 07/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
CS is HIGH between valid commands; Address
inputs are switching every two clock cycles;
Data bus inputs are stable
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH;
switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle;
CKE = HIGH; CS = HIGH;
are switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH;
switching; Data bus inputs are stable
Active power-down standby current: Clock stopped; One bank
active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: One bank active; CKE = HIGH;
CS = HIGH;
switching; Data bus inputs are stable
Active nonpower-down standby: Clock stopped; One bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Operating burst read: One bank active; BL = 4; CL = 3;
t
inputs are switching every two clock cycles; 50 percent data
changing each burst
Operating burst write: One bank active; BL = 4;
Continuous WRITE bursts; Address inputs are switching; 50 percent
data changing each burst
Auto refresh: Burst refresh; CKE = HIGH;
Address and control inputs are switching; Data
bus inputs are stable
Deep power-down current: Address and control pins are stable;
Data bus inputs are stable
RC =
CK =
t
t
RC (MIN);
CK (MIN); Continuous READ bursts; I
t
t
CK =
CK =
I
Notes: 1–5 apply to all parameters/conditions in this table; notes appear on page 19;
V
DD
DD
t
CK =
t
t
/V
t
CK (MIN); Address and control inputs are
CK (MIN); Address and control inputs are
Specifications and Conditions (x32)
CK =
DD
Q = 1.70–1.95V
t
CK (MIN); CKE is HIGH;
t
t
CK (MIN); Address and control inputs are
CK =
t
CK (MIN); Address and control inputs
OUT
= 0mA; Address
t
CK =
t
t
RFC
RFC =
JEDEC-standard
Reduced page-
size option
t
CK (MIN);
=
option
138ns
t
REFI
18
Symbol
I
I
I
I
I
I
I
I
I
DD
DD
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
I
DD
DD
DD
DD
DD
DD
I
DD
DD
I
I
DD
DD
DD
2NS
3NS
2PS
3PS
4W
2N
3N
5A
3P
4R
2P
0
5
8
1Gb: x16, x32 Mobile DDR SDRAM
110
150
150
140
80
18
14
20
16
15
-5
105
145
145
140
-54
75
17
13
19
15
15
Electrical Specifications
Max
600
600
3.6
3.6
10
100
140
140
140
©2007 Micron Technology, Inc. All rights reserved
70
15
18
14
15
-6
8
120
120
140
-75
70
60
12
16
12
14
8
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
10, 11
7, 13
7, 8
10
6
6
7
9
9
8
6
6
6
6