mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 38

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef82ce3074/Source: 09005aef82cd0158
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. G 07/08 EN
Notes:
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted (for example, the cur-
3. Current state definitions:
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
5. All states and sequences not shown are illegal or reserved.
6. Requires appropriate DM masking.
7. A WRITE command may be applied after the completion of the READ burst; otherwise, a
3b. The minimum delay from a READ or WRITE command with auto precharge enabled to a
3a. The read with auto precharge enabled or write with auto precharge enabled states can
the previous state was self refresh), after
down, or a full initialization if the previous state was deep power-down).
rent state is for bank n and the commands shown are those supported for issue to bank m,
assuming that bank m is in such a state that the given command is supported). Exceptions
are covered in the notes below.
Idle:
Row active:
Read:
Write:
are idle.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
each be broken into two parts: the access period and the precharge period. For read
with auto precharge, the precharge period is defined as if the same burst was executed
with auto precharge disabled and then followed with the earliest possible PRECHARGE
command that still accesses all of the data in the burst. For write with auto precharge,
the precharge period begins when
was disabled. The access period starts with registration of the command and ends where
the precharge period (or
This device supports concurrent auto precharge such that when a read with auto pre-
charge is enabled or a write with auto precharge is enabled, any command to other
banks is supported, as long as that command does not interrupt the read or write data
transfer already in process. In either case, all other related limitations apply (for exam-
ple, contention between read data and write data must be avoided).
command to a different bank is summarized below.
From Command
WRITE w/AP
READ w/AP
The bank has been precharged, and
A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated and has not yet terminated or been
terminated.
A WRITE burst has been initiated and has not yet terminated or been
terminated.
To Command
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
n - 1
38
t
RP) begins.
was HIGH and CKE
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR ends, with
t
XP has been met (if the previous state was power-
1Gb: x16, x32 Mobile DDR SDRAM
n
is HIGH and after
(with Concurrent Auto Precharge)
t
WR measured as if auto precharge
t
RP has been met.
[1 + (BL/2)]
t
Minimum Delay
RCD has been met. No data
©2007 Micron Technology, Inc. All rights reserved
[CL + (BL/2)]
(BL/2) ×
(BL/2)
1
1
1
1
t
XSR has been met (if
t
t
t
t
CK
CK
CK
CK
t
CK +
t
CK
t
CK
Operations
t
CK
t
WTR