mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 87

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Revision History: Commands, Operations, and Timing Diagrams
Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/08
Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/08
Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/07
Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .07/07
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08_rev_hist__5.fm - Rev. G 07/08 EN
• Table 17, “Truth Table – Current State Bank n – Command to Bank m,” on page 37:
• “Auto Precharge” on page 74: Added third paragraph regarding
• Figure 46: “Bank Write – Without Auto Precharge,” on page 78: Corrected note 4.
• “Functional Description” on page 28, Figure 18: “Extended Mode Register,” on
• Table 19, “Burst Definition Table,” on page 45: Added BL 16 content.
• “Output Drive Strength” on page 47: Added three-quarter drive strength and deleted
• Figure 18: “Extended Mode Register,” on page 48: Removed E7 column and updated
• Updated note 2:
• Updated note 3:
• Removed former final note in each case:
• Figure 42: “WRITE-to-PRECHARGE – Odd Number of Data, Interrupting,” on page 73:
• “Concurrent Auto Precharge” on page 74: Updated figure references.
• Figure 18: “Extended Mode Register,” on page 48: Updated to include mid-strength
• Figure 20: “Status Register Definition,” on page 50: Corrected headings for density.
• Initial release.
Corrected note 3b, changed “disabled” to “enabled.”
page 48, and throughout document as appropriate: Added BL 16.
one-eighth drive strength. Updated to include 37 ohm (deleted 100 ohm).
valid column heading to E7–E0; expanded driver strength section to include three-
quarter drive strength.
– Figure 22: “Consecutive READ Bursts,” on page 53
– Figure 23: “Nonconsecutive READ Bursts,” on page 54
– Figure 24: “Random READ Accesses,” on page 55
– Figure 25: “Terminating a READ Burst,” on page 56
– Figure 27: “READ-to-PRECHARGE,” on page 58
– Figure 26: “READ-to-WRITE,” on page 57
– Figure 36: “Random WRITE Cycles,” on page 67:
– Figure 38: “WRITE-to-READ – Interrupting,” on page 69
– Figure 39: “WRITE-to-READ – Odd Number of Data, Interrupting,” on page 70
– Figure 41: “WRITE-to-PRECHARGE – Interrupting,” on page 72
Extended
driver information.
Revision History: Commands, Operations, and Timing Diagrams
t
WR to coincide with T5 transition.
87
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x16, x32 Mobile DDR SDRAM
©2007 Micron Technology, Inc. All rights reserved
t
RAS lock-out.