tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 109

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

9.3.4
Table 9-5 PWM Output Mode
DV7CK = 0
fc/2
NORMAL1/2, IDLE1/2 mode
fc/2
fc/2
fc/2
fc/2
11
up-counter counts up using the internal clock.
er F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the tim-
er F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The
INTTCj interrupt request is generated at this time.
erated. Upon reset, the timer F/Fj is cleared to 0.
be changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the
INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immediate-
ly after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output, the
value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the read-
ing data of PWREGj is previous value until INTTCj is generated.
fs
fc
[Hz]
8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)
7
5
3
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stop-
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the
Note 4: j = 3, 4
This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The
When a match between the up-counter and the PWREGj value is detected, the logic level output from the tim-
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be gen-
(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the inter-
rupt request occur at the same time, an unstable value is shifted, that may result in generation of the
pulse different from the programmed value until the next INTTCj interrupt request is generated.
ped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3 ; Stops the timer.
CLR (TCjCR).7 ; Sets the PWMj pin to the high level.
STOP mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a
pulse is output from the PWMj pin during the warm-up period time after exiting the STOP mode.
Source Clock
DV7CK = 1
fs/2
fc/2
fc/2
fc/2
fc/2
3
fs
fc
[Hz]
7
5
3
SLOW1/2,
SLEEP1/2
fs/2
mode
3
fs
-
-
-
-
-
[Hz]
fc = 16 MHz
Page 91
30.5 μs
62.5 ns
128 μs
500 ns
125 ns
8 μs
2 μs
Resolution
fs = 32.768 kHz
244.14 μs
30.5 μs
-
-
-
-
-
fc = 16 MHz
32.8 ms
2.05 ms
7.81 ms
512 μs
128 μs
32 μs
16 μs
Repeated Cycle
TMP86FH46BNG
fs = 32.768 kHz
62.5 ms
7.81 ms
-
-
-
-
-