tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 50

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.2
Interrupt enable register (EIR)
Example 1 :Clears interrupt latches
Example 2 :Reads interrupt latches
Example 3 :Tests interrupt latches
3.2
3.2.1
3.2.2
ble interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt).
Non-maskable interrupt is accepted regardless of the contents of the EIR.
isters are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions
(Including read-modify-write instructions such as bit manipulation or operation instructions).
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
Interrupt enable register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maska-
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These reg-
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual inter-
rupt enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled.
When an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maska-
ble interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked
data, which was the status before interrupt acceptance, is loaded on IMF again.
tion. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is in-
itialized to “0”.
ing bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to
“0” disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized
to “0” and all maskable interrupts are not accepted until they are set to “1”.
Interrupt master enable flag (IMF)
Individual interrupt enable flags (EF15 to EF4)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruc-
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the correspond-
clear IMF to "0"
on the EF or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normal-
ly on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating
EF or IL should be executed before setting IMF="1".
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be
sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required af-
ter operating on the EF or IL (Enable interrupt by EI instruction)
DI
LDW
EI
LD
TEST
JR
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating
(ILL), 1110100000111111B
WA, (ILL)
(ILL). 7
F, SSET
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; IMF ← 0
; IL12, IL10 to IL6 ← 0
; IMF ← 1
; W ← ILH, A ← ILL
; if IL7 = 1 then jump
TMP86FH46BNG