tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 34

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.2
System Clock Controller
2.2.4
2.2.4.1
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of periph-
Operating Mode Control
put (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR).
mode is started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
ted with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releasing
STOP mode in edge-sensitive mode.
erals may be set after IDLE0 or SLEEP0 mode is released.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2). How-
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external in-
(1)
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup in-
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selec-
STOP mode
STOP2 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the
main power supply is cut off and long term battery backup.
STOP5 to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts im-
mediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the pro-
gram to first confirm that the STOP pin input is low and STOP5 to STOP2 input is high. The follow-
ing two methods can be used for confirmation.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to
Even if an instruction for starting STOP mode is executed while STOP pin input is high or
Level-sensitive release mode (RELM = “1”)
ever, because the STOP pin is different from the key-on wakeup and can not inhibit the release in-
put, the STOP pin must be used for releasing STOP mode.
terrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately af-
ter STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before en-
abling interrupts after STOP mode is released, clear unnecessary interrupt latches.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
status in effect before STOP mode was entered.
which started STOP mode.
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TMP86FH46BNG