tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 73

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tmp86fh46bng

Manufacturer Part Number
tmp86fh46bng
Description
8 Bit Microcontroller Tlcs-870/c Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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6.2.5
Clock
Binary counter
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
(WDTCR1<WDTOUT>= "1")
WDT reset output
request is generated. When a watchdog timer reset request is generated, the RESET pin outputs a low-level sig-
nal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 μs @ fc = 16.0 MHz).
Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc
(high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals
have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be consid-
ered as an approximate value because it has slight errors.
Figure 6-2 Watchdog Timer Interrupt/Reset
1
Write 4E
2
H
to WDTCR2
3
2
17
/fc
0
Page 55
(High-Z)
1
2
19
/fc [s]
2
3
A reset occurs
TMP86FH46BNG
0
(WDTT=11)

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