tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 53

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.3
3.4
3.4.1
Interrupt source selector
(003EH)
INTSEL
the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt
requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL reg-
ister must be set appropriately before interrupt requests are generated.
to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 μs @16 MHz) af-
ter the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt re-
turn instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the tim-
ing chart of interrupt acceptance processing.
Interrupt Source Selector (INTSEL)
Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable
The following interrupt sources share their interrupt source level; the source is selected on the register INTSEL.
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared
Interrupt Sequence
1. INT4 and INTTXD share the interrupt source level whose priority is 15.
2. INT5 and INTADC share the interrupt source level whose priority is 16.
Interrupt acceptance processing is packaged as follows.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any fol-
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt mas-
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vec-
e. The instruction stored at the entry address of the interrupt service program is executed.
7
-
lowing interrupt.
ter enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Mean-
while, the stack pointer (SP) is decremented by 3.
tor table, is transferred to the program counter.
IL14ER
IL15ER
6
-
5
-
Selects INT4 or INTTXD
Selects INT5 or INTADC
4
-
3
-
Page 35
2
-
IL14ER
1
IL15ER
0: INT4
1: INTTXD
0: INT5
1: INTADC
0
(Initial value: **** **00)
TMP86FH46BNG
R/W
R/W