PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 150

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2480/2580/4480/4580
11.1
Timer0 can operate as either a timer or a counter; the
mode
(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 11.3 “Prescaler”). If
the TMR0 register is written to, the increment is inhib-
ited for the following two instruction cycles. The user
can work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
FIGURE 11-2:
DS39637A-page 148
T0CKI pin
Note:
Note:
is
Timer0 Operation
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
T0CS
T0PS2:T0PS0
PSA
selected
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
F
OSC
/4
T0SE
T0CS
T0PS2:T0PS0
PSA
F
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
by
OSC
0
1
/4
clearing
Programmable
0
1
Prescaler
the
3
Programmable
Prescaler
T0CS
3
1
0
Preliminary
bit
(2 T
Sync with
1
0
Internal
Clocks
CY
Delay)
(2 T
internal phase clock (T
synchronization and the onset of incrementing the
timer/counter.
11.2
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
Sync with
Internal
Clocks
CY
Delay)
Timer0 Reads and Writes in
16-Bit Mode
TMR0L
8
8
8
TMR0L
OSC
High Byte
 2004 Microchip Technology Inc.
TMR0H
8
TMR0
8
). There is a delay between
8
8
on Overflow
Internal Data Bus
Internal Data Bus
TMR0IF
Read TMR0L
Write TMR0L
Set
on Overflow
TMR0IF
Set