PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 169

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

15.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (ECCP1M3:ECCP1M0). At the same time,
the interrupt flag bit ECCP1IF is set.
15.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 15-2:
 2004 Microchip Technology Inc.
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2 compare output latch (depending
on device configuration) to the default low
level. This is not the PORTC I/O data
latch.
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
ECCPR1H
TMR1H
TMR3H
CCPR1H
T3CCP1
Comparator
Comparator
ECCPR1L
CCPR1L
TMR1L
TMR3L
Compare
Compare
Match
Match
PIC18F2480/2580/4480/4580
1
0
Set CCP1IF
Preliminary
T3ECCP1
Set CCP1IF
(Timer1/Timer3 Reset, A/D Trigger)
15.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP interrupt is generated, if enabled
and the CCP1IE bit is set.
15.3.4
Both CCP modules are equipped with a special event
trigger. This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The special event trigger is enabled by selecting the
Compare
(CCP1M3:CCP1M0 = 1011).
For either CCP module, the special event trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows
programmable period register for either timer.
Special Event Trigger
Special Event Trigger
ECCP1CON<3:0>
CCP1CON<3:0>
(Timer1 Reset)
Output
Output
Logic
4
Logic
4
the
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
CCPRx
S
R
S
R
Q
Q
registers
Event
Output Enable
Output Enable
TRIS
TRIS
DS39637A-page 167
to
Trigger
ECCP1 pin
CCP1 pin
serve
as
mode
a