PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 236

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2480/2580/4480/4580
18.1.3
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 18-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN bus Sync character)
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and a high bit time in
order to minimize any effects caused by asymmetry of
the incoming signal. After a Start bit, the SPBRG
begins counting up, using the preselected clock source
on the first rising edge of RX. After eight bits on the RX
pin or the fifth rising edge, an accumulated value total-
ling
SPBRGH:SPBRG register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 18-2).
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 18-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
DS39637A-page 234
the
AUTO-BAUD RATE DETECT
proper
BRG
period
is
left
in
Preliminary
the
TABLE 18-4:
18.1.3.1
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensure
that ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.
Note:
BRG16
Note 1: If the WUE bit is set with the ABDEN bit,
0
0
1
1
2: It is up to the user to determine that the
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.
BRGH
Auto-Baud Rate Detection will occur on
the byte following the Break character.
incoming character baud rate is within the
range of the selected BRG clock source.
Some
frequency and EUSART baud rates are
not possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when
Detection feature.
ABD and EUSART Transmission
0
1
0
1
BRG COUNTER
CLOCK RATES
using
combinations
 2004 Microchip Technology Inc.
BRG Counter Clock
the
F
F
F
F
OSC
OSC
OSC
OSC
Auto-Baud
/512
/128
/128
/32
of
oscillator
Rate