PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 369

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

25.1.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
W
W
Q1
STANDARD INSTRUCTION SET
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
=
=
10h
25h
ADD Literal to W
ADDLW
0
(W) + k
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed
in W.
1
1
literal ‘k’
ADDLW
Read
0000
Q2
k
255
15h
W
k
1111
Process
Data
Q3
kkkk
Write to W
PIC18F2480/2580/4480/4580
Q4
kkkk
Preliminary
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
ADD W to f
ADDWF
0
d
a
(W) + (f)
N, OV, C, DC, Z
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ADDWF
Read
0010
Q2
17h
0C2h
0D9h
0C2h
f
[0,1]
[0,1]
255
dest
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
DS39637A-page 367
95 (5Fh). See
ffff
destination
Write to
Q4
ffff