PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 318

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2480/2580/4480/4580
REGISTER 23-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER
DS39637A-page 316
Mode 1, 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Mode 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
IRXIE: CAN Invalid Received Message Interrupt Enable bit
1 = Enable invalid message received interrupt
0 = Disable invalid message received interrupt
WAKIE: CAN bus Activity Wake-up Interrupt Enable bit
1 = Enable bus activity wake-up interrupt
0 = Disable bus activity wake-up interrupt
ERRIE: CAN bus Error Interrupt Enable bit
1 = Enable CAN bus error interrupt
0 = Disable CAN bus error interrupt
When CAN is in Mode 0:
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1 = Enable Transmit Buffer 2 interrupt
0 = Disable Transmit Buffer 2 interrupt
When CAN is in Mode 1 or 2:
TXBnIE: CAN Transmit Buffer Interrupts Enable bit
1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0
0 = Disable all transmit buffer interrupts
TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit
1 = Enable Transmit Buffer 1 interrupt
0 = Disable Transmit Buffer 1 interrupt
TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit
1 = Enable Transmit Buffer 0 interrupt
0 = Disable Transmit Buffer 0 interrupt
When CAN is in Mode 0:
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1 = Enable Receive Buffer 1 interrupt
0 = Disable Receive Buffer 1 interrupt
When CAN is in Mode 1 or 2:
RXBnIE: CAN Receive Buffer Interrupts Enable bit
1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0
0 = Disable all receive buffer interrupts
When CAN is in Mode 0:
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1 = Enable Receive Buffer 0 interrupt
0 = Disable Receive Buffer 0 interrupt
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIE: FIFO Watermark Interrupt Enable bit
1 = Enable FIFO watermark interrupt
0 = Disable FIFO watermark interrupt
R/W-0
R/W-0
IRXIE
IRXIE
Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.
WAKIE
WAKIE
R/W-0
R/W-0
ERRIE
ERRIE
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
Preliminary
TXB2IE
TXBnIE
R/W-0
R/W-0
TXB1IE
TXB1IE
R/W-0
R/W-0
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
(1)
TXB0IE
TXB0IE
R/W-0
R/W-0
 2004 Microchip Technology Inc.
(1)
(1)
RXB1IE
RXBnIE
R/W-0
R/W-0
x = Bit is unknown
FIFOWMIE
RXB0IE
R/W-0
R/W-0
bit 0