PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 375

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PC
No
Q1
Read literal
operation
Unconditional Branch
BRA
-1024
(PC) + 2 + 2n
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1
2
HERE
1101
No
‘n’
Q2
=
=
n
n
address (HERE)
address (Jump)
1023
0nnn
BRA
operation
Process
Data
No
PC
Q3
Jump
nnnn
Write to PC
operation
PIC18F2480/2580/4480/4580
No
Q4
nnnn
Preliminary
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Bit Set f
BSF
0
0
a
1
None
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
BSF
Read
1000
Q2
=
=
f
b
[0,1]
f<b>
f, b {,a}
255
7
0Ah
8Ah
FLAG_REG, 7, 1
bbba
Process
Data
Q3
DS39637A-page 373
95 (5Fh). See
ffff
register ‘f’
Write
Q4
ffff