PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 400

• Manufacturer Part Number: PIC18F2480
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2480/2580/4480/4580
SUBWFB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
DS39637A-page 398
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
Subtract W from f with Borrow
SUBWFB
0
d
a
(f) – (W) – (C)
N, OV, C, DC, Z
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
SUBWFB
SUBWFB REG, 0, 0
SUBWFB
Read
0101
Q2
f
[0,1]
[0,1]
19h
0Dh
1
0Ch
0Dh
1
0
0
1Bh
1Ah
0
1Bh
00h
1
1
0
03h
0Eh
1
F5h
0Eh
0
0
1
255
10da
REG, 1, 0
REG, 1, 0
f {,d {,a}}
(0001 1001)
(0000 1101)
(0000 1011)
(0000 1101)
; result is positive
(0001 1011)
(0001 1010)
(0001 1011)
; result is zero
(0000 0011)
(0000 1101)
(1111 0100)
; [2’s comp]
(0000 1101)
; result is negative
Process
Data
dest
Q3
95 (5Fh). See
ffff
destination
Write to
Q4
ffff
Preliminary
SWAPF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Swap f
SWAPF f {,d {,a}}
0
d
a
(f<3:0>)
(f<7:4>)
None
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
SWAPF
Read
0011
Q2
53h
35h
f
[0,1]
[0,1]
 2004 Microchip Technology Inc.
255
REG, 1, 0
dest<7:4>,
dest<3:0>
10da
Process
Data
Q3
95 (5Fh). See
ffff
destination
Write to
Q4
ffff