PIC18F2480 MICROCHIP [Microchip Technology], PIC18F2480 Datasheet - Page 408

no-image

PIC18F2480

Manufacturer Part Number
PIC18F2480
Description
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2480-E/ML
Manufacturer:
MICROCHIP
Quantity:
1 001
Part Number:
PIC18F2480-E/SO
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F2480-I/SO
Manufacturer:
Microchi
Quantity:
9 999
Part Number:
PIC18F2480-I/SO
Manufacturer:
MIC
Quantity:
20 000
Part Number:
PIC18F2480-I/SO
0
Part Number:
PIC18F2480-I/SP
Manufacturer:
TDK
Quantity:
64
Part Number:
PIC18F2480-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F2480/2580/4480/4580
MOVSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (dest.)
Description
Words:
Cycles:
Example:
DS39637A-page 406
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
Contents
of 86h
FSR2
Contents
of 85h
Contents
of 86h
Q1
source addr
Determine
Determine
dest addr
Move Indexed to Indexed
MOVSS [z
0
0
((FSR2) + z
None
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a
2
2
MOVSS
1110
1111
Q2
z
z
=
=
=
=
=
=
s
d
127
127
80h
33h
11h
80h
33h
33h
[05h], [06h]
s
s
source addr
1011
xxxx
)
], [z
Determine
Determine
dest addr
d
((FSR2) + z
Q3
]
s
’ or ‘z
1zzz
xzzz
d
source reg
to dest reg
’,
NOP
d
)
Read
Write
Q4
zzzz
zzzz
.
Preliminary
s
d
PUSHL
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2H:FSR2L
Memory (01ECh)
FSR2H:FSR2L
Memory (01ECh)
Q1
Store Literal at FSR2, Decrement FSR2
PUSHL k
0
k
FSR2 – 1
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2 is
decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
1
1
1111
k
(FSR2),
Read ‘k’
PUSHL
255
Q2
 2004 Microchip Technology Inc.
FSR2
1010
08h
=
=
=
=
Process
data
Q3
01ECh
00h
01EBh
08h
kkkk
destination
Write to
Q4
kkkk

Related parts for PIC18F2480